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VDPBF16PS

Converts packed bfloat16 floating-point values to packed single-precision floating-point values. The instruction converts each bfloat16 value in the source to a 32-bit single-precision float by appending zeros to the mantissa.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available only in 64-bit mode or compatibility mode. It requires the AVX-512 BF16 extension.

The instruction performs a widening conversion; therefore, the destination register must be large enough to hold the resulting single-precision floats. If the source is a ZMM register, the operation is performed on the lower half of the register to accommodate the increase in bit-width per element. Failure to account for the element size increase may result in accessing unexpected register lanes.