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VCVTTPH2UDQ

Converts the packed signed 16-bit floating-point values (half-precision) from the source operand to packed unsigned 64-bit integers in the destination operand. The conversion is performed using the truncation rounding-mode.

The following table covers the supported source and destinations.

DO NOT support LOCK

This instruction is available only in 64-bit mode. It requires the AVX-512 extension (specifically AVX-512 FP16) to be supported by the processor.

The result of the conversion is based on the truncation rounding-mode regardless of the current rounding-mode setting in the MXCSR register. If the source value is NaN or exceeds the range of a u64, the result is the indefinite integer value ($2^{64}-1$). The operation may trigger #O or #P exceptions depending on the precision and magnitude of the input value.