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VCVTTPH2DQ

Converts packed half-precision floating-point values to packed signed 64-bit integers. The conversion is performed by rounding the half-precision floating-point value to the nearest signed integer using the rounding mode specified in the immediate operand.

The following table specifies the supported source and destination operands.

DO NOT support LOCK

The instruction requires the AVX support bit to be enabled in the CPU. It is not available in compatibility mode for 32-bit operating systems if the AVX bit is not set.

The immediate operand MUST be used to specify the rounding mode; if the immediate is not provided, the instruction is invalid. Failure to specify a valid rounding mode will result in a general protection fault or invalid opcode exception.

Because the destination is a 64-bit integer (qword) and the source is a 16-bit float (word), the instruction expands the data. Consequently, only the lower 128 bits of the destination xmm register are updated, and only two half-precision values from the source are converted to two 64-bit integers. This leads to a partial update of the destination register if the source contains more than two elements.

If the converted value is too large to be represented as a signed 64-bit integer, the result is the integer representation of the indefinite value, and #O is signaled.