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VCVTTPD2QQ

Converts packed double-precision floating-point values to packed signed 64-bit integers with truncation.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available only in 64-bit mode. It requires the AVX feature set to be enabled.

The conversion uses the truncation rounding mode regardless of the current rounding control in the MXCSR register. If the result is too large to be represented as an i64, the destination contains the indefinite integer value (i64 min value). If the input is a Signaling NaN, #S is signaled; if it is a Quiet NaN, the destination is set to the indefinite integer value. Precision (#P) is signaled if the result is not exact.