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VCVTQQ2PS

Converts packed signed qword integers to a packed single-precision floating-point vector. Each 64-bit signed integer element from the source is converted to a 32-bit floating-point element in the destination.

The following table covers the supported source and destinations:

DO NOT support LOCK

This instruction is available only in 64-bit mode. It requires the AVX-512 foundation.

The destination register is overwritten; therefore, the source register must not be the same as the destination if the value is needed after the operation. The conversion follows the rounding mode specified in the MXCSR register. If the signed integer value cannot be represented exactly in the destination floating-point format, the result is rounded according to the current rounding mode, potentially triggering #P.