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VCVTQQ2PH

Converts a signed 64-bit integer to a half-precision floating-point number. The instruction converts the signed integer value in the source operand to a 16-bit floating-point format and stores the result in the destination operand.

The following table covers the supported source and destination operands:

DO NOT support LOCK

This instruction is only available when the processor is operating in 64-bit mode. It requires AVX-512 support (specifically AVX-512F).

The conversion follows the rounding mode specified in the MXCSR register. If the result cannot be represented within the half-precision format, the following exceptions may be raised: #O for overflow or #P if the result is inexact. Values that are too small to be represented as normalized half-precision numbers may result in #U.