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Converts packed single-precision floating-point values to packed signed 64-bit integers. The conversion is performed using the rounding mode specified in the MXCSR register.

The following table describes the supported source and destination operands:

DO NOT support LOCK

This instruction is only available in 64-bit mode. It requires AVX-512 support.

The destination register is overwritten. Because the output elements (i64) are twice the size of the input elements (f32), only the first two elements of the source xmm register are converted and stored in the destination xmm register. Attempting to use this instruction in 32-bit compatibility mode SHALL result in an invalid opcode exception.

If the converted value is too large or too small to be represented as an i64, the result is the integer value corresponding to the indefinite value, and #O is signaled. Denormal inputs are handled according to the MXCSR settings, potentially signaling #D. Inexact results SHALL signal #P.