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Converts packed half-precision floating-point values to unsigned quadword integers. The instruction converts each half-precision value in the source to an unsigned 64-bit integer using the rounding mode specified in the MXCSR register.

The table below covers what the source and destinations can be.

DO NOT support LOCK

This instruction is only available in 64-bit mode. It requires AVX-512 and the AVX-512 FP16 extension.

The conversion follows the rounding mode set in the MXCSR register. If the value is NaN, the result is the indeterminate value. If the value is too large to be represented as a u64, the result is the maximum representable u64 value, and a #O exception is generated. Precision loss during conversion triggers a #P exception.