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VCVTPH2PSX

Converts packed half-precision floating-point values to packed single-precision floating-point values with a specified rounding mode.

The following table covers the supported source and destination operands.

DO NOT support LOCK

This instruction SHALL be used only in 64-bit mode or 32-bit mode. It is NOT supported in compatibility mode. The instruction requires AVX-512 FP16 extensions to be enabled.

The rounding mode is controlled by the immediate operand, which overrides the rounding control in the MXCSR register. Failure to provide a valid immediate value results in an invalid operation. Precision (#P) and Underflow (#U) exceptions may be triggered based on the conversion result and the active rounding mode.