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VCVTPH2PS

Converts packed half-precision floating-point values to packed single-precision floating-point values.

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available only in 64-bit mode or 32-bit mode. It requires the SSE3 and AVX instruction sets to be supported by the processor.

The instruction converts two 16-bit floating-point values (f16) from the source to two 32-bit floating-point values (f32) in the destination. If the source is an xmm register, only the lower 32 bits of the destination register are updated in the non-AVX version, or the destination is overwritten based on the specific VEX encoding.

When converting from half-precision to single-precision, no precision loss occurs; however, if the source value is a signaling NaN, a #P exception may be generated depending on the MXCSR register settings. Users MUST ensure that the destination register is properly initialized if utilizing the instruction in a way that does not overwrite the entire register.