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VCVTPH2DQ

Converts packed half-precision floating-point values to packed signed 64-bit integers. The conversion is performed by rounding to the nearest integer using the rounding-control mode currently set in the MXCSR register.

The following table describes the supported source and destination operands.

DO NOT support LOCK

This instruction is only available when the processor is operating in 64-bit mode or compatibility mode. It requires the AVX-512 FP16 instruction set extension.

If the converted value is too large to be represented as an i64, the result is the maximum or minimum representable signed 64-bit integer. If the input is a NaN, the result is the integer minimum value (i64 min). These operations MAY trigger #O or #P based on the rounding and precision of the conversion.