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VCVTPD2UDQ

Convert packed double-precision floating-point values to packed unsigned 64-bit integers. The instruction truncates the floating-point values toward zero.

The following table covers what the source and destinations can be:

DO NOT support LOCK

The instruction requires AVX support. It operates on XMM registers and is available in 64-bit mode and compatibility mode.

If the source value is NaN, the destination is set to the indefinite integer value (all bits set to 1). If the source value is too large to be represented as a u64, #O is signaled and the destination is set to the maximum u64 value. Precision #P is signaled if the result is not exact. All operations are subject to the rounding control in the MXCSR register, though truncation is the default behavior for this specific opcode.