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VADDSH

Adds two packed signed 16-bit integers from the first source operand and the second source operand, and stores the result in the destination operand. The operation is performed using saturation arithmetic; results that exceed the range of a signed 16-bit integer are clamped to the maximum or minimum representable signed 16-bit value.

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available only in 64-bit mode or compatibility mode. It requires the SSE4.1 instruction set extension to be supported by the processor.

The instruction operates on packed 16-bit elements; therefore, it does not affect the EFLAGS register. Ensure that the input data is properly aligned to 16-byte boundaries when using memory operands to avoid performance degradation or alignment check exceptions.