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VADDPH

Adds packed signed 16-bit floating-point values from two sources and stores the result in a destination.

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available only in 64-bit mode or 32-bit mode. It is NOT supported in compatibility mode.

The instruction requires the AVX-512 F (Foundation) instruction set to be enabled. If the destination register is the same as one of the source registers, the operation is performed in-place.

To avoid unexpected behavior, ensure that the destination register is properly zero-extended if using YMM or ZMM registers to prevent leakage of stale data from the upper bits of the register. Results are subject to the floating-point control word (FCW) settings for rounding and precision.