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V4FNMADDPS

Multiplies four pairs of single-precision floating-point numbers from two source operands, subtracts the result from a third source operand, and stores the result in the destination operand.

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction SHALL be used only in 64-bit mode or compatibility mode. It REQUIRES the AVX instruction set extension.

The destination register SHALL be aligned to a 16-byte boundary if memory operands are used to avoid general protection faults. The operation is subject to floating-point exceptions #P, #O, #U, #D, and #I based on the MXCSR register settings. Precision is handled according to the IEEE 754 standard for single-precision floating-point numbers.