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TESTUI

Performs a logical AND operation between the source operand and the destination operand, then sets the Zero Flag (ZF) in the RFLAGS register if the result is zero; otherwise, it clears ZF. The destination operand is not modified.

The table below covers the supported source and destination operands.

DO NOT support LOCK

This instruction is available only in 64-bit mode. It is NOT supported in compatibility mode or 32-bit mode.

The destination operand MUST be a register. Attempts to use a memory operand as the destination SHALL result in an encoding error or invalid opcode exception. Since this instruction does not modify the destination operand, it is primarily used for conditional branching based on bitmasking.