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TDPBSUD
This instruction updates the Table Descriptor Base Address and the Table Descriptor Size in the specified descriptor table register.
The following table describes the supported source and destination operands.
| source | destination(s) |
|---|---|
| reg | reg |
| imm | #I |
| mN | #I |
DO NOT support LOCK
This instruction is ONLY available in 64-bit mode. It is NOT supported in compatibility mode or 32-bit protected mode.
The instruction MUST be executed with CPL 0. If the current privilege level is not 0, a general protection fault (#GP) SHALL be generated. The destination register MUST be one of the supported descriptor table registers (GDTR, IDTR, PDTR, or LDTR). Attempts to use an unsupported register as a destination SHALL result in an invalid opcode exception.