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SIDT

Stores the contents of the Interrupt Descriptor Table Register (IDTR) into the specified memory destination.

The table below covers what the source and destinations can be.

DO NOT support LOCK

The instruction is available in both 64-bit mode and compatibility mode. In 64-bit mode, the instruction stores a 10-byte value consisting of a 16-bit IDT limit and a 64-bit base address. In compatibility mode, it stores a 6-byte value consisting of a 16-bit limit and a 32-bit base address.

The destination operand MUST be a memory location. Use of a register as a destination will result in an invalid operation. When executing in 64-bit mode, the memory destination MUST be aligned to avoid potential performance penalties or exceptions depending on the alignment check (AC) flag in CR0.