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SHLD

SHLD shifts a double precision value formed by two operands to the left. The bits shifted out of the destination operand are shifted into the source operand. The number of bits to shift is specified by a third operand.

The following table covers what the source and destinations can be.

DO NOT support LOCK

SHLD is available in 64-bit mode, 32-bit mode, and 16-bit mode. In 64-bit mode, the instruction supports 8-bit, 16-bit, 32-bit, and 64-bit operand sizes.

If the shift count is specified as an immediate and is greater than or equal to the operand size, the instruction SHALL behave according to the operand size; specifically, for 32-bit operands, the shift count is masked to 5 bits (modulo 32). If the shift count is provided in a register, it is similarly masked. Failure to account for this masking MAY result in unexpected shift amounts when the register value exceeds the operand bit-width.