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SHL
Shifts the destination operand to the left by the number of bits specified by the source operand. Vacant bits are filled with zeros, and the last bit shifted out of the MSB is moved into the CF flag.
The following table covers what the source and destinations can be.
| source | destination(s) |
|---|---|
| imm | rN |
| reg | rN |
| reg | mN |
DO NOT support LOCK
The instruction is available in 64-bit mode, compatibility mode, and 32-bit mode. When the destination is a 64-bit register, the shift count is masked to 6 bits (0-63) if the source is a register.
If the shift count is equal to or greater than the operand size, the result is defined as zero and CF is undefined. Users SHOULD ensure the shift count is within the range of the operand size to maintain predictable CF behavior. When using an immediate value for the shift count, it MUST be a constant.