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SHA256RNDS2

Performs two rounds of the SHA-256 message schedule update. It operates on the provided xmm registers to update the SHA-256 hash state using the specified constants and current state values.

The table below covers the supported source and destination operands.

DO NOT support LOCK

This instruction is only available in 64-bit mode or 32-bit mode when the Intel SHA Extensions are supported by the processor. It requires the use of XMM registers; any attempt to use general-purpose registers or memory operands directly as the primary operands for the transformation logic will result in an invalid opcode.

The instruction requires that the input XMM registers are properly initialized with the correct SHA-256 state and message schedule data. Failure to align the data according to the SHA-256 specification before execution will result in incorrect hash computations without triggering an architectural exception. All operands MUST be XMM registers.