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SHA1RNDS4

Performs the SHA-1 round operations on the provided operands. It calculates the SHA-1 message schedule and state update for four rounds, updating the state registers based on the SHA-1 algorithm specifications.

The table below covers the supported source and destination operands.

DO NOT support LOCK

This instruction is available only in 64-bit mode and compatibility mode. It requires the processor to support the SHA extensions.

The instruction operates specifically on XMM registers. Using this instruction on a processor that does not support the SHA extension will result in an invalid opcode exception. Ensure the CPUID leaf 07h.1:ED bit is set before execution.