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SHA1MSG2

SHA1MSG2 performs the second step of the SHA-1 message schedule. It computes the sum of three 32-bit values, applies a right rotate of 7 bits to the result, and XORs the result with a fourth 32-bit value.

The following table covers the supported source and destination operands.

DO NOT support LOCK

This instruction is only available when the processor is in 64-bit mode or compatibility mode. It requires the processor to support the SHA extensions.

The instruction operates on 128-bit XMM registers. To avoid incorrect results, the programmer MUST ensure that the input XMM registers contain valid 32-bit words aligned with the SHA-1 specification, as the operation is performed on the four 32-bit elements within the registers. Failure to manage the data layout within the xmm registers will lead to logic errors in the message schedule calculation.