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SHA1MSG1

This instruction performs a SHA-1 message schedule update. It computes the sum of three 32-bit words and rotates the result, updating the state of the SHA-1 message schedule.

The table after the description covers what the source and destinations can be.

DO NOT support LOCK

This instruction is only available when the processor is operating in 64-bit mode or compatibility mode. It requires the processor to support the SHA extensions.

The operands MUST be XMM registers. Attempting to use other register types or memory operands SHALL result in an invalid opcode exception. This instruction operates on 32-bit doublewords within the XMM registers; ensure that the data is aligned to 128-bit boundaries to avoid performance penalties.