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PSRLQ

Shifts the destination operand to the right by the count specified in the source operand. The vacated bit positions are filled with zeros.

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available only in 64-bit mode. In compatibility mode, this instruction is not supported and will trigger an invalid opcode exception.

The shift count is masked to 6 bits (0 to 63). If the source operand is a register, only the low-order 6 bits of the register are used to determine the shift count. Providing a value greater than 63 will not shift the operand by that value, but by the result of the value modulo 64.