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PSRLDQ

Shifts the unsigned quadword value in the source operand to the right by the count specified in the low-order 6 bits of the ecx register. Zeroes are shifted into the most significant bits.

The table after the description covers what the source and destinations can be.

DO NOT support LOCK

The instruction SHALL only be used in 64-bit mode. In compatibility mode, this instruction is not supported and will trigger an invalid opcode exception.

The shift count is exclusively determined by the value in ecx. The instruction ignores the upper 58 bits of the rcx register. Users MUST ensure the shift count is loaded into ecx before execution to avoid unpredictable results stemming from stale data in the register.