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PSLLW

Shifts each 16-bit packed signed integer element of the destination operand to the left by the count specified in the source operand.

The table after the description covers what the source and destinations can be.

DO NOT support LOCK

This instruction is only available when the processor is operating in 64-bit mode or compatibility mode.

The shift count is masked to 15 bits; if the source register contains a value greater than 15, only the lower 4 bits (0-15) are used. To avoid unexpected behavior, the shift count should be constrained to a value between 0 and 15.