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PSLLQ

Shifts the 64-bit quadword value in the destination operand to the left by the number of bits specified by the source operand. Vacant bit positions are filled with zeros.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is only available in 64-bit mode. It is NOT supported in compatibility mode.

The shift count is masked to 6 bits (0-63) for the PSLLQ instruction. If the source operand is a register, only the low-order 6 bits of the register are used; any bits beyond the 6th bit are ignored. This prevents undefined behavior when a value greater than 63 is provided.