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PMAXUW

Compares two unsigned word operands and stores the maximum value in the destination.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available only in 64-bit mode or compatibility mode. It requires the SSE4.1 extension set to be supported by the processor.

The destination register must be a 128-bit XMM register. Operations on word-sized elements within the XMM registers are performed in parallel (SIMD). Failure to align memory operands to 2-byte boundaries may result in performance degradation or faults depending on the alignment check (AC) flag in the EFLAGS register.