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PHADDW

Adds two packed signed 16-bit integers from two source operands and stores the resulting sums in the destination. For each pair of 16-bit elements, the result is the sum of the corresponding elements from the sources.

The following table describes the supported source and destination operands.

DO NOT support LOCK

This instruction is only available in 64-bit mode or 32-bit mode when SSE3 is supported. It operates on XMM registers; it is NOT available in compatibility mode for operands exceeding the size of the current execution mode's register width if the specific SSE3 extension is absent.

The instruction performs signed addition. Since it does not utilize a saturation mechanism, integer overflow will result in wrap-around behavior according to two's complement arithmetic. Users MUST ensure that the input values do not exceed the range of i16 to avoid unintended wrap-around results.