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PEXT

Extracts bits from the first operand according to the bitmask specified by the second operand. For each bit set to 1 in the mask, the corresponding bit from the source is extracted and packed into the destination in contiguous low-order positions.

The table after the description covers what the source and destinations can be.

DO NOT support LOCK

PEXT is available only if the processor supports the BMI2 instruction set. It is supported in 64-bit mode and compatibility mode. The operation is performed on the lower 32 or 64 bits of the registers depending on the operand size.

To avoid undefined behavior or incorrect results, ensure that the mask operand does not contain bits set beyond the operand size. Note that on certain processor families (specifically AMD Zen 2 and earlier), PEXT is implemented in microcode and may exhibit significantly higher latency compared to Intel implementations.