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PCMPEQQ

Compares two 64-bit quadword integers from the source and destination operands for equality. If the quadwords are equal, the corresponding 64 bits of the destination register are set to 1; otherwise, they are set to 0.

The table after the description covers what the source and destinations can be.

DO NOT support LOCK

This instruction is only available when the processor is operating in 64-bit mode or compatibility mode. It requires the SSE4.1 instruction set extension or higher.

The destination register MUST be an XMM, YMM, or ZMM register. Using this instruction with unsupported register widths or in 32-bit mode SHALL result in an invalid opcode exception. When using YMM or ZMM registers, the operation is performed as a SIMD parallel comparison across the vector width.