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PADDD

Adds two packed signed 32-bit integers from the source and destination operands, storing the result in the destination.

The following table covers the supported source and destination operands.

DO NOT support LOCK

This instruction is only available when the processor is operating in 64-bit mode or compatibility mode. It requires the SSE3 extension set to be enabled.

The operation performs a signed addition of packed i32 values. If an overflow occurs for any of the individual 32-bit elements, the result wraps around according to two's complement arithmetic. This instruction does not set any flags in the EFLAGS register.