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MINSS

Subtracts a scalar single-precision floating-point value from another scalar single-precision floating-point value, storing the result in the destination operand. This instruction operates on the lowest 32 bits of the XMM registers.

The following table describes the supported source and destination operands.

DO NOT support LOCK

This instruction is available in 64-bit mode and compatibility mode. It requires SSE support.

The instruction ignores the upper 31 bits of the XMM registers. If the memory operand is not aligned to a 4-byte boundary, a general-protection exception may occur depending on the alignment check (AC) flag in the EFLAGS register. Precision control is governed by the MXCSR register; specifically, the rounding mode determines how results are handled for #P (Inexact result) and #U (Numeric underflow).