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MINPS

Subtracts the minimum of two packed single-precision floating-point values from each corresponding element of two XMM operands.

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available in 64-bit mode and compatibility mode. It requires SSE support.

The destination register must be a 128-bit XMM register. Memory operands MUST be 16-byte aligned to avoid general protection faults or alignment check exceptions.

The operation follows the IEEE 754 standard for floating-point arithmetic. It may trigger floating-point exceptions including #P, #O, #U, or #D depending on the input values and the MXCSR register settings.