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LMSW

Loads the lower 16 bits of the source operand into the lower 16 bits of the SWAP register (CR0).

The following table describes the supported source and destination operands.

DO NOT support LOCK

This instruction is only available in compatibility mode or when operating in a 32-bit protected mode environment. It is not supported in 64-bit mode.

Execution of this instruction REQUIRES CPL 0. If the current privilege level is greater than 0, the processor SHALL generate a general-protection exception (#GP).