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LDTILECFG

Loads the tile configuration from a memory location into the internal tile configuration registers.

The table below covers what the source and destinations can be.

DO NOT support LOCK

This instruction is only available when the processor supports AMX (Advanced Matrix Extensions). It SHALL only be executed in CPL 0 or when the CR0.AMX bit is set to 1, otherwise, it SHALL trigger a General Protection Exception (#GP).

The memory location pointed to by the source operand SHALL be aligned on a 64-byte boundary; failure to do so SHALL result in an alignment check exception (#AC) if alignment check is enabled, or a general protection exception (#GP). Users SHALL ensure the memory region contains a valid tilecfg structure to avoid undefined behavior in subsequent TDPBSSD or TDPBSSW operations.