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INVLPG

Invalidates the translation lookaside buffer (TLB) entry for a specific virtual address.

The table after the description covers what the source and destinations can be.

DO NOT support LOCK

The instruction is available in 64-bit mode and compatibility mode. It REQUIRES that the address be a valid linear address. The instruction does not affect the TLB entries of other processors; therefore, in a multiprocessor system, a "TLB shootdown" MUST be implemented via software to invalidate entries across all cores.

The operand MUST be a memory address; providing an immediate or register directly as the operand is not supported by the opcode. If the address is not present in the page tables, the instruction executes without effect. Failure to invalidate the TLB after modifying a page table entry MAY lead to the processor using stale translation data, resulting in unpredictable memory access or protection faults.