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HSUBPD

Subtracts two double-precision floating-point packed values. The instruction subtracts the second operand from the first and stores the result in the destination.

The following table specifies the supported source and destination operands.

DO NOT support LOCK

This instruction is available in 64-bit mode and 32-bit mode. It requires the SSE2 instruction set extension to be supported by the processor.

Ensure that the destination register is not used as a source for other simultaneous operations if the result is needed for subsequent calculations. This instruction operates on packed data; if the input vectors are not properly aligned to 16-byte boundaries when using memory operands, a general protection exception (#GP) may occur depending on the specific processor implementation and memory alignment checks.