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HADDPS

Adds corresponding elements of two packed single-precision floating-point vectors, then performs a horizontal add of the adjacent pairs of elements within each resulting vector.

The following table covers the supported source and destination operands:

DO NOT support LOCK

This instruction is available in 64-bit mode and compatibility mode. It requires the SSE3 instruction set extension to be supported by the processor.

The destination register is overwritten by the result; therefore, the destination register cannot be used as a source operand if the original values must be preserved.

The operation is subject to the floating-point control word settings in the MXCSR register. Specifically, the rounding mode determines how results are rounded. If an operation results in an overflow, it SHALL trigger #O; if it results in a loss of precision, it SHALL trigger #P. Denormalized operands SHALL trigger #D.