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FISTP
Stores an extended-precision floating-point value from the top of the ST(0) register to a memory location and pops the ST(0) register.
The following table covers what the source and destinations can be:
| source | destination(s) |
|---|---|
| f80 | m10 |
DO NOT support LOCK
This instruction is available in both 64-bit mode and compatibility mode. It operates exclusively on the x87 Floating-Point Unit (FPU) register stack.
The destination memory operand MUST be aligned to the appropriate boundary to avoid potential performance penalties or alignment exceptions depending on the processor configuration. The value is stored as an 80-bit extended-precision floating-point number. If the destination memory region is not exactly 10 bytes, it MAY result in an out-of-bounds memory access.
The instruction MAY trigger the following exceptions:
- #O: Numeric overflow.
- #U: Numeric underflow.
- #P: Inexact result (precision).