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DIVSS

Divides a scalar single-precision floating-point value by another scalar single-precision floating-point value. The result is stored in the destination operand.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available in 64-bit mode and 32-bit mode. It requires SSE support.

The instruction follows the IEEE 754 standard for floating-point arithmetic. If the divisor is zero, it SHALL trigger #Z. If the result cannot be represented within the destination precision, it SHALL trigger #P. The precision and rounding control are governed by the MXCSR register.