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DIVSD

Divides the scalar double-precision floating-point value in the destination operand by the scalar double-precision floating-point value in the source operand.

The table below covers what the source and destinations can be.

DO NOT support LOCK

The instruction is available in 64-bit mode and compatibility mode. It requires the SSE unit to be present.

The destination register MUST be an XMM register. If the result is too large to be represented in the destination format, #O is signaled. If the divisor is zero, #Z is signaled. If the result is too small to be represented, #U is signaled. Precision exceptions #P may occur if the result requires rounding. All operations are subject to the rounding mode and exception mask settings in the MXCSR register.