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CVTTPS2DQ

Converts packed single-precision floating-point values to packed signed integers with quadwords using truncation.

The following table specifies the supported source and destination operands.

DO NOT support LOCK

This instruction is only available in 64-bit mode or compatibility mode. It requires the AVX instruction set extension to be supported by the processor.

The conversion uses truncation toward zero. If the source value is NaN, the result is the integer minimum value (i64 minimum). If the source value is too large to be represented as a signed 64-bit integer, the result is the integer minimum value (i64 minimum).

The destination register is overwritten by the resulting i64 values; however, since the source consists of four f32 values and the destination consists of two i64 values, only the lower 128 bits of the destination xmm register are updated. Specifically, the first two f32 elements of the source are converted to the two i64 elements of the destination. The upper two f32 elements of the source are ignored.

#P may be signaled.