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CVTSS2SI

Converts a scalar single-precision floating-point value to a signed integer. The conversion is performed by truncating the fraction (rounding toward zero).

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction requires SSE3 support. In 64-bit mode, the destination register can be either a 32-bit or 64-bit general-purpose register. If a 32-bit register is specified, the result is truncated to i32; if a 64-bit register is specified, the result is sign-extended to i64.

If the converted value is too large to be represented in the destination integer type, the instruction SHALL signal #O and the destination register SHALL be set to the indefinite integer value (maximum or minimum representable value for the target size, depending on the sign). If the source is a Signaling NaN, #I SHALL be signaled. Precision #P is signaled if the result is rounded.