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CVTSI2SD

Converts a signed integer source to a double-precision floating-point destination. The signed integer is sign-extended to 64 bits and then converted to a double-precision floating-point format.

The table after the description covers what the source and destinations can be.

DO NOT support LOCK

The instruction SHALL be used in 64-bit mode or compatibility mode. It requires the SSE3 instruction set extension to be supported by the processor.

The source operand MUST be a 32-bit signed integer. If a 64-bit integer conversion is required, the CVTSI2SD instruction is insufficient as it only supports dword sources; the CVTSI2SD variant for 64-bit integers is not the same opcode. Failure to use the correct operand size for the intended integer width WILL result in incorrect value conversion due to the 32-bit restriction of this specific mnemonic. No floating-point exceptions (#I, #Z, #D, #O, #U, #P) are generated by this instruction.