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COMISD

Compares two scalar-precision floating-point values. The instruction compares the value in the source operand with the value in the destination operand and sets the EFLAGS register (CF, ZF, PF) based on the result of the comparison.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available in 64-bit mode and compatibility mode. It requires the SSE2 instruction set to be supported by the processor.

If either operand is a Signaling NaN, a floating-point exception is raised. If one operand is a Quiet NaN and the other is not, or if both are Quiet NaNs, the ZF, PF, and CF flags are all set to 1 to indicate an unordered comparison. The user MUST check the PF flag to distinguish between an unordered result (NaN) and a "equal" result.