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CMPPS

Compares the packed single-precision floating-point values in the first operand with the packed single-precision floating-point values in the second operand. The comparison is performed according to the specified predicate, and the results are stored in the destination operand as masks.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available in 64-bit mode and compatibility mode. It requires the SSE instruction set to be supported by the processor.

The behavior of the comparison depends on the immediate byte (predicate) provided. If the predicate is invalid, the instruction will trigger an invalid operation exception (#I). The instruction does not modify the EFLAGS register. All operations are performed on packed values; therefore, the source and destination MUST be 128-bit XMM registers or aligned memory regions to avoid performance penalties or faults.