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CLWB

Writes a modified cache line back to main memory without changing the cache line's state (it remains in the Modified state if it was already modified), provided the line is present in the cache.

The following table covers what the source and destinations can be:

DO NOT support LOCK

The instruction is only available in 64-bit mode. It is not supported in compatibility mode.

CLWB is a hint to the processor; the hardware MAY ignore the request to write back the cache line. To ensure the data is persisted to the memory controller, a SFENCE instruction SHALL be executed after CLWB. This instruction does not evict the line from the cache, unlike CLFLUSH.