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CLFLUSH

Invalidates the cache line containing the specified linear address from all levels of the processor cache and writes any modified data back to system memory.

The table below covers what the source and destinations can be.

DO NOT support LOCK

The instruction requires a linear address. It operates regardless of the current privilege level; however, the address must be present in the page tables. If the address is not present, the instruction does not trigger a page fault but simply does not flush the cache line. It is supported in 64-bit mode, 32-bit mode, and compatibility mode.

To ensure that the data is flushed and visible to other processors or devices, the programmer SHOULD follow the CLFLUSH instruction with an SFENCE or MFENCE instruction, as CLFLUSH is not ordered with respect to other memory operations. Failure to do so MAY result in memory inconsistency in multi-processor environments.